1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof. More specifically, the present invention relates to a structure of an EEPROM (Electrically Erasable and Programmable Read Only Memory) and manufacturing method thereof.
2. Description of the Background Art
Conventionally, an EEPROM which allows programming of data freely and allows electrical writing and erasing of information has been known as one of the non-volatile semiconductor memory devices. The EEPROM has a source region, a drain region and a control gate electrode. These are arranged in various manners. An EEROM has been known in which an impurity region extending in one direction provided at the surface of a semiconductor substrate is used as the source and drain regions for miniaturization.
The structure of such an EEPROM will be described in the following.
FIG. 29 is a cross section of the EEPROM described in Japanese Patent Laying-Open No. 8-107158. Referring to FIG. 29, a memory cell transistor 500 constituting the EEPROM includes an Si substrate 511, a source region 515a, a drain region 515b, polycrystalline Si films 521a, 521b and a silicide film 526b as the floating gate electrode, and a polycrystalline Si film 523 as a control gate electrode.
Source and drain regions 515a and 515b formed in Si substrate 511 are formed to extend from this side to the depth side of the sheet. Control gate electrode 523 extends from the right to the left direction of FIG. 29, that is, in the direction crossing the direction of extension of the source and drain regions 515a and 515b. 
An SiO2 film 514 in a pattern of element isolating region is formed on Si substrate 511. An SiO2 film 517 as a gate oxide film is formed on the surface of Si substrate 511. Polycrystalline Si film 521a constituting the floating gate electrode is formed on SiO2 film 517. Silicide film 526b is formed on polycrystalline Si film 521a. 
Silicide film 526a is formed on the surfaces of source and drain regions 515a and 515b . 
An SiO2 film 525 is formed on a sidewall of polycrystalline Si film 521a. On Si substrate 511, an interlayer insulating film 527 is formed. Polycrystalline Si film 521b constituting the floating gate electrode is formed on interlayer insulating film 527. An ONO film 522 including a stack of an oxide film, a nitride film and an oxide film is formed on polycrystalline Si film 521b. Polycrystalline Si film 523 as the control gate electrode is formed on ONO film 522.
In such an EEPROM, source and drain regions 515a and 515b are formed by impurity regions extending in one direction at the surface of Si substrate 511. Therefore, the number of interconnection layers can be reduced as compared with such EEPROMs in which the source and drain regions are formed in the shape of islands which are connected by interconnection layers. Therefore, the EEPROM of the above described type is suitable for miniaturization. IEDM86, pp. 592 to 595 describes an EPROM (Electrically Programmable Read Only Memory) in which impurity regions extending in one direction are used as source and drain regions.
In such an EEPROM as shown in FIG. 29, presence/absence of information (data) is determined dependent on whether electrons are stored or not in the floating gate electrode constituted by polycrystalline Si film 521a, 521b and silicide film 526b. 
When electrons are injected in the floating gate electrode, the threshold voltage of memory cell transistor 500 assumes a high value of Vthp. This state is referred to as a programmed state. In this state, data xe2x80x9c0xe2x80x9d is stored in memory cell transistor 500.
The electrons accumulated in the floating gate electrode do not dissipate but are kept semi-permanently, and therefore the stored data is held semi-permanently.
When electrons are not accumulated in the floating gate electrode, the threshold value of memory cell transistor 500 attains to a low value of Vthe. This state is referred to as an erased state. In this state, data xe2x80x9c1xe2x80x9d is stored in memory cell transistor 500. By detecting these two states, data stored in memory cell transistor 500 can be read.
The operation of memory cell transistor 500 shown in FIG. 29 will be described.
At the time of programming, a positive high voltage Vpp (typically about 20V) is applied to control gate electrode 523. Si substrate 511, source region 515a and drain region 515b are set to the ground potential. Accordingly, electrons gather in the channel region formed between the source and drain regions 515a and 515b, which electrons are injected to the floating gate electrode by tunneling phenomenon. As a result, the threshold voltage of memory cell transistor 500 attains higher to Vthp.
Among memory cell transistors not selected at the time of programming, in that one which shares control gate electrode 523 with memory cell transistor 500, a high voltage of about 20V is applied to control gate electrode 523, a voltage of about 7 volt is applied to the drain region, the source region is set to the floating state and the substrate is set to the ground potential.
At the time of erasure, a negative high voltage Vpp (typically about xe2x88x9220V) is applied to control gate electrode 523, and source region 515a, drain region 515b and Si substrate 512 are set to the ground potential. Accordingly, the electrons which have been stored in the floating gate electrode are discharging by the tunneling phenomenon to Si substrate 511. As a result, the threshold voltage of memory cell transistor 500 lowers to Vthe.
In a reading operation of selected memory cell transistor 500, assuming that Vthe less than 3.3V less than Vthp, 3.3V is applied to control gate electrode 523 and drain region 515b. Source region 515a and Si substrate 511 are set to the ground potential.
The threshold voltage Vthp in the programmed state is higher than 3.3V, and therefore in the programmed state, no current flows between the source and drain regions 515a and 515b. As the threshold voltage Vthp in the erased state is smaller than 3.3V, current flows between source and drain regions 515a and 515b in the erased state.
At the time of reading, in the non-selected memory cell transistor, the control gate electrode is set to the ground potential, 3.3V is applied to the drain region, and the source region and the Si substrate are set to the ground potential. At this time, since the threshold voltages Vthp and Vthe are generally larger than 0V, no current flows between the source and drain regions of the memory cell transistor if the voltage applied to the control gate electrode is 0V.
In the above described memory cell transistor, during the process of heating for forming SiO2 film 514 on Si substrate 511, SiO2 film 514 tends to extend in the direction of the longer side. Thereafter, SiO2 film 514 is cooled and tends to contract in the longer side direction.
In the step of thermal diffusion for forming source and drain regions 515a and 515b, the source and drain regions 515a and 515b tend to extend in the direction of the longer side. Thereafter, the source and drain regions 515a and 515b tend to contract in the direction of the longer side. This causes tensile or compressive stress to Si substrate 511. Accordingly, crystal defect results in the channel region between the source and drain regions 515a and 515b. A crystal defect tends to occur when stress remains in the  less than 110 greater than  direction. Since arsenic which is implanted in the source or drain region 515a or 515b is trapped in the crystal defect, the distance (channel length) between the source and drain regions 515a and 515b is made shorter. When such a memory cell transistor is selected and the voltage of 3.3V is applied to the drain region 515b, a current always flows because of punch through between the source and drain regions 515a and 515b, regardless of the threshold voltage of the memory cell transistor. Therefore, even if the memory cell transistor is in the programmed state, current flows between the source and drain regions 515a and 515b, resulting in erroneous detection of information.
When a crystal defect exists in the channel region, SiO2 film 517 as the gate oxide film formed on the channel region is also prone to crystal defects. When there is a crystal defect in SiO2 film 517, SiO2 film 517 experiences dielectric breakdown when electrons are discharged from the floating gate electrode to Si substrate 511 through SiO2 film 517, or when electrons are injected from Si substrate 511 to the floating gate electrode through SiO2 film 517. This leads to a problem of shorter life of rewriting. Further, there is also a problem that the charges which have been accumulated in the floating gate electrode leak through SiO2 film 517 to Si substrate 511, so that charges cannot be retained.
Further, in the transistor not selected at the time of programming and sharing control gate electrode 523 with the selected memory cell transistor, a high voltage of about 20V is applied to control gate electrode 523, a voltage of about 7V is applied to the drain region, the source region is set to the floating state and Si substrate is set to the ground potential.
At this time, as Si substrate 511 is of p type and drain region 511b is of n type, the p-n junction at the interface between Si substrate 511 and drain region 515b is biased in reverse direction. Therefore, a depletion layer extends from the interface toward the Si substrate 511.
When there is a crystal defect in the channel region and the depletion layer extends to reach the crystal defect, electron-hole pairs generate from the crystal defect. The generated electrons are accelerated toward control gate electrode 523 to which the high voltage of about 20V is applied. The accelerated electrons passes through SiO2 film 517 and injected in the floating gate electrode. This phenomenon is a writing to a non-selected memory cell transistor, which is generally referred to as xe2x80x9cdrain disturbxe2x80x9d.
When such a phenomenon occurs, a non-selected memory cell transistor is programmed, and therefore accurate writing of information becomes impossible.
The present invention was made to solve the above described problems, and its object is to provide a non-volatile semiconductor memory device allowing accurate reading of information, superior in life of rewriting and charge retention characteristic, and free of the so called drain disturb phenomenon, as well as to provide a manufacturing method of such a semiconductor memory device.
The non-volatile semiconductor memory device in accordance with the present invention includes a semiconductor substrate, a plurality of strip shaped isolating insulation films, a plurality of strip shaped impurity regions, a floating gate electrode and a control gate electrode.
The semiconductor substrate has a main surface. The plurality of strip shaped isolating insulation films are formed on the main surface of the semiconductor substrate extending continuously and approximately along the  less than 100 greater than  direction. The plurality of strip shaped impurity regions are provided between the plurality of isolating insulation films, and formed on the main surface of the semiconductor substrate extending continuously and approximately along the  less than 100 greater than  direction. The floating gate electrode is provided between the impurity regions, and formed on the main surface of the semiconductor substrate with a first dielectric film interposed. The control gate electrode is formed on the floating gate electrode with a second dielectric film interposed.
Here, the  less than 100 greater than  direction represents a direction equivalent to [100], and more specifically, it includes [xe2x88x92100], [010], [0xe2x88x9210], [001] and [00xe2x88x921] directions. Here, a negative number of Miller index is represented by xe2x80x9cxe2x88x921xe2x80x9d.
In the non-volatile semiconductor memory device structured as described above, both the impurity region and the isolating insulation film extend along the  less than 100 greater than  direction. Accordingly, the impurity regions and the isolating insulation films tend to expand or contract along the  less than 100 greater than  direction when heated/cooled during formation. Therefore, stress remains in the semiconductor substrate along the  less than 100 greater than  direction. In the semiconductor substrate, the  less than 100 greater than  direction is less susceptible to crystal defect such as dislocation even when there remains stress, as compared with other directions, for example, compared with the cleavage direction of  less than 100 greater than . Therefore, generation of crystal defect in the channel region formed between adjacent impurity regions is suppressed. This means that leakage current caused by punch through is not generated in the channel region. Accordingly, accurate reading of information is possible when the non-volatile semiconductor memory device is read.
Further, as there is no crystal defect in the channel region, there is no crystal defect generated in the first dielectric film formed on the channel region, either. Therefore, dielectric breakdown of the first dielectric film can be prevented when the electrons are injected from the semiconductor substrate to the floating gate through the first dielectric film or when the electrons are drawn out from the floating gate electrode to the semiconductor substrate through the first dielectric film. As a result, the life of rewriting is improved, and charge retention characteristic of the floating gate electrode is improved.
In a memory cell transistor not selected at the time of programming, a high voltage is applied to the control gate electrode, a low voltage is applied to the impurity region (drain region) and the semiconductor substrate is set to the ground potential. In this state, even when a depletion layer generates at the interface between impurity region and semiconductor substrate and the depletion layer extends to the channel region, electron-hole pairs do not generate in the channel region, as there is no crystal defect in the channel region. Therefore, even when a high voltage is applied to the control gate electrode, electrons are not passed through the first dielectric film to be injected to the floating gate electrode. Therefore, programming of the non-selected memory cell transistor is prevented. Namely, the so called drain disturb phenomenon can be prevented. It is not clearly disclosed or suggested in the aforementioned Japanese Patent Laying-Open No. 8-107158 and IEDM86, pp. 592 to 595 that in the non-volatile semiconductor memory devices described therein, the isolating oxide film and the impurity regions are formed along the  less than 100 greater than  direction, and therefore the above described effects cannot be attained.
Preferably, the impurity region contains boron or arsenic. When the impurity region contains boron, the impurity region containing boron has smaller lattice constant than the semiconductor substrate, and therefore it tends to apply compressive stress to the semiconductor substrate. Further, the strip shaped isolating insulation films formed sandwiching the impurity regions apply tensile stress to the semiconductor substrate. Therefore, the compressive stress from the impurity region and the tensile stress from the isolating insulation film cancel each other. As a result, the semiconductor substrate is less susceptible to any stress, and hence generation of crystal defects can be prevented.
When the impurity region contains arsenic, the impurity region containing arsenic has approximately equal lattice constant as the semiconductor substrate, and therefore is does not cause any strain in the semiconductor substrate. Therefore, generation of crystal defects can be prevented.
Further, on the main surface of the semiconductor substrate, preferably, a plurality of trenches are formed extending continuously and approximately along the  less than 100 greater than  direction, with each of the isolating insulation films filled in each of the trenches. As trenches are formed on the main surface of the semiconductor substrate and isolating insulation films are filled in the trenches as described above, the non-volatile semiconductor memory device can further be miniaturized.
Further, preferably, the semiconductor substrate is formed of a single crystal of an element having a diamond type structure.
Further, the semiconductor substrate preferably includes silicon.
The floating gate electrode preferably includes a plurality of floating gate electrodes formed spaced from each other approximately along the  less than 100 greater than  direction.
Further, the isolating insulation films and the impurity regions preferably extend parallel to each other.
Preferably, the control gate electrode includes a plurality of control gate electrodes extending continuously along a certain direction, and the direction of extension of the isolating insulation films and the impurity regions is approximately orthogonal to the direction of extension of the control gate electrodes. This allows formation of many memory cell transistors in a small space, and the non-volatile semiconductor memory device can be miniaturized.
A non-volatile semiconductor memory device in accordance with another aspect of the present invention includes a semiconductor substrate, a plurality of strip shaped isolating insulation films, a plurality of strip shaped impurity regions, a floating gate electrode and a control gate electrode.
The semiconductor substrate has a main surface. The plurality of strip shaped isolating insulation films are formed on the main surface of the semiconductor substrate extending continuously approximately along the  less than 100 greater than  direction. The plurality of strip shaped impurity regions are provided between the plurality of isolating insulation films, and formed on the main surface of semiconductor substrate extending parallel to the direction of extension of the plurality of isolating insulation films, the floating gate electrode is provided between the plurality of impurity regions, and formed on the main surface of the semiconductor substrate with a first dielectric film interposed. The control gate electrode is formed on the floating gate electrode with a second dielectric film interposed.
The floating gate electrode includes a plurality of floating gate electrodes formed spaced from each other, approximately along the  less than 100 greater than  direction. The control gate electrode includes a plurality of control gate electrodes formed extending continuously along a certain direction. The direction of extension of the isolating insulation films and the impurity regions is approximately orthogonal to the direction of extension of the control gate electrodes.
In the non-volatile semiconductor memory device structured as described above, the impurity regions and the isolating insulation films both extend approximately along the  less than 100 greater than  direction. Therefore, the impurity regions and the isolating insulation films tend to expand or contract along the  less than 100 greater than  direction when heated/cooled during formation. Therefore, stress remains in the semiconductor substrate along the  less than 100 greater than  direction. In the semiconductor substrate, the  less than 100 greater than  direction is less susceptible to generation of crystal defects such as dislocation even when stress is applied, as compared with other directions, for example, the cleavage direction of  less than 100 greater than . Therefore generation of the crystal defect in the channel region formed between adjacent impurity regions can be suppressed. Therefore, leakage current caused by punch through in the channel region is suppressed, enabling accurate reading of information.
As there is no crystal defect in the channel region, there is no crystal defect generated in the first dielectric film formed on the channel region. Therefore, dielectric breakdown of the first dielectric film can be prevented when electrons are injected from the semiconductor substrate to the floating gate electrode through the first dielectric film or when the electrons are drawn out from the floating gate electrode to the semiconductor substrate through the first dielectric film. As a result, life of rewriting of the non-volatile semiconductor memory device is improved, and the charge retention characteristic is also improved.
Further, in a non-selected memory cell transistor at the time of programming, a high voltage is applied to the control gate electrode and a low voltage is applied to the impurity region (drain region) and the substrate is set to the ground potential. In this state, even when a depletion layer generates at the interface between the impurity region and the semiconductor substrate and the depletion layer extends to the channel region, electron-hole pairs do not generate in the channel region, as there is no crystal defect in the channel region. Therefore, even when a high voltage is applied to the control gate electrode, electrons are not passed through the first dielectric film to be injected to the floating gate electrode. Therefore, the so called drain disturb phenomenon at the time of programming can be prevented.
The method of manufacturing a non-volatile semiconductor memory device in accordance with the present invention includes the following steps.
(1) Forming a plurality of strip shaped isolating insulation films on a main surface of a semiconductor substrate to extend continuously and approximately along the  less than 100 greater than  direction.
(2) Forming a plurality of strip shaped impurity regions between the plurality of the isolating insulation films on the main surface of the semiconductor substrate extending continuously and approximately along the  less than 100 greater than  direction.
(3) Forming a plurality of strip shaped first conductive layers between the plurality of impurity regions to extend continuously and approximately along the  less than 100 greater than  direction on the main surface of the semiconductor substrate, with a first dielectric film interposed.
(4) Forming a second conductive layer on the first conductive layer with a second dielectric film interposed.
(5) Etching the first and second conductive layers to form a floating gate electrode on the main surface of the semiconductor substrate with the first dielectric film interposed, and forming a control gate electrode on the floating gate electrode with the second dielectric film interposed.
In the method of manufacturing the non-volatile semiconductor memory device including the above described steps, in the step (3), the strip shaped impurity regions, the isolating insulation films and the first conductive layers are formed approximately along the  less than 100 greater than  direction. Therefore, stress remains in the semiconductor substrate along the  less than 100 greater than  direction by heating/cooling when these layers are formed. The  less than 100 greater than  direction of the semiconductor substrate is less susceptible to generation of crystal defects such as dislocation as compared with other directions, for example, the cleavage direction of  less than 110 greater than . Therefore, generation of crystal defects in the channel region formed between adjacent impurity regions can be suppressed. Accordingly, leakage current caused by punch through in the channel region can be prevented, and therefore accurate reading of information is possible.
Further, as there is no crystal defect in the channel region, there is no crystal defect generated in the first dielectric film formed on the channel region. As a result, even when the non-volatile semiconductor memory device is used for a long period of time, the first dielectric film is free of dielectric breakdown, and therefore life of rewriting and charge retention characteristic are improved.
Further, as there is no crystal defect generated in the channel region, in the non-selected memory cell transistor at the time of programming, even when there is a reverse bias between the impurity region and semiconductor substrate and a depletion layer extends to the channel region, electron-hole pairs do not generate as there is no crystal defect in the channel region. Therefore, even when a high voltage is applied to the control gate electrode, electrons are not passed through the first dielectric film to be injected to the floating gate electrode. As a result, the so called drain disturb phenomenon can be prevented.
Preferably, the step of forming the control gate electrode includes the step of forming a plurality of strip shaped control gate electrodes to extend continuously in a direction approximately orthogonal to the direction of extension of the first conductive layers. Here, as the direction of the control gate electrodes is approximately orthogonal to the direction of extension of the first conductive layers, many control gate electrode can be formed in a small space. Therefore, the non-volatile semiconductor memory device can further be miniaturized.
Further, preferably, the step of forming the floating gate electrode includes the step of forming a plurality of floating gate electrode spaced from each other approximately along the  less than 100 greater than  direction.
Further, the step of forming the plurality of isolating insulation films preferably includes forming a plurality of isolating insulation films using a semiconductor substrate having a notch indicating the  less than 100 greater than  direction. As a substrate having a notch indicating the  less than 100 greater than  direction is used, the semiconductor substrate can be positioned aligned with the  less than 100 greater than  direction. Therefore, the non-volatile semiconductor memory device in accordance with the present invention can be manufactured utilizing the conventional apparatus.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.